The present invention relates to the field of MOSFET's, and more particularly to a method for fabricating complementary enhancement and high threshold depletion mode field effect transistors on a single substrate.
Devices such as are taught in U.S. Pat. No. 5,027,171, "Dual Polarity MOS Analog Memory Device," and U.S. Pat. No. 5,097,156, "Compensation Circuitry for Analog Multiplier" employ both enhancement and high threshold depletion mode transistors in analog integrated circuits. The operational characteristics of the two types of devices are sufficiently different that their fabrication generally requires incompatible processing steps. For example, high transconductance of the enhancement mode transistors is generally desirable in applications such as amplifier circuits, while high threshold characteristics for depletion mode transistors are desirable in applications such as analog multipliers. To maximize the transconductance, the thickness of the insulating gate layer of the enhancement mode device is minimized, whereas to achieve the maximum threshold voltage, the thickness of the insulating gate layer of a depletion mode device is relatively high. In order to fabricate depletion and enhancement mode transistors on a single substrate, conventional MOSFET fabrication techniques would normally result in a single gate oxide thickness that would not produce depletion and enhancement transistors having optimal performance characteristics. Because there are applications requiring the use of both such transistors, there is therefore, a need for a method for manufacturing complementary depletion and enhancement mode transistors on a single substrate.